Microprocessors are designed to handle events, such as communication line status and errors, through the use of interrupts. Typically, when a microprocessor receives an event, hardware in the microprocessor sets a bit in an alarm register associated with that particular event. For each bit in the alarm register there is also a corresponding bit in an interrupt mask register that determines if that bit in the alarm register will contribute to or cause the microprocessor to be interrupted. If the bit in the alarm register for that event is allowed to cause an interrupt (not masked), then the microprocessor will be interrupted.
Once the microprocessor is interrupted, the software that processes the interrupts has to determine the cause of the interrupt and inform high-level application software. For example, the interrupt software may have to look at every alarm register and its associated interrupt mask register to determine if a bit within that particular alarm register caused the interrupt. Once the bit causing the interrupt is determined, the interrupt software would have to determine which high-level application software is associated with processing that type of interrupt and then notify that particular high-level application software. However, if the cause of the interrupt is not determined and passed off to the application software within a certain period of time, the event that caused of the interrupt may be lost or the microprocessor might incur unacceptable delays in processing.
As microprocessors have become more specialized and/or capable of monitoring and controlling more devices, the number of interrupts has also increased. However, a simple alarm register and an interrupt mask register structure could not accommodate all of the interrupts needed. In response, system designers developed interrupt register structures that allowed multiple interrupt bits (e.g., bits in the alarm register) to be combined into a single bit in another register. For example, one alarm register containing 16 bits could be combined into a single bit in another alarm register and so one.
These new interrupt register structures, however, are not without problems. Once such problem is the ability of the interrupt software to traverse through the interrupt register structure to determine what caused the interrupt. Also, for each interrupt structure, software engineers would have to develop special code just to traverse that particular structure. The software engineers would also have to develop specialized software applications to handle the interrupts for that interrupt register structure. This would cause the source code to become huge and unmanageable. Also, with the increased code size, the source code can become error prone and validation of both the hardware and software becomes an issue. In addition, as the number of hardware interrupts increases, the ability of the software to detect and handle the increased number of interrupts becomes more difficult.
Accordingly, what is needed in the art is a way to overcome the deficiencies of the prior art in handling complex interrupt structures.